State machines built from integrated circuits on semiconductor substrates need to be radioactively hardened to prevent soft error events that occur when a high energy ionizing radiation particle travels through the semiconductor substrate. This is particularly true if the state machine is to operate in high radiation environments such as outer space. An ionizing particle traveling through the semiconductor substrate may cause a transient voltage glitch, i.e., a single event transient (SET), that may be captured by a sequential state storage element or may cause a sequential state element (SSE) to transition to an erroneous state, i.e., a single event upset (SEU) when in the feedback mode.
One technique for ameliorating the effects of high energy radiation is to provide hardening elements and/or redundancy in the SSE. Hardening elements either correct, or operate to allow the SSE to correct upsets, or prevent the SSE from transitioning erroneously, due to radiation strikes. For example, hardening elements can require agreement between redundant bit signals, isolate critical nodes from one another, and/or delay error propagation, thereby allowing the SSE to make corrections or not to transition to an erroneous state. To provide an example of hardening through redundancy, some SSEs employ Dual Interlocked Cells (DICE) with multiple interlocked nodes so that a radiation strike on any one of the interlocked nodes is corrected using the other interlocked node or nodes. However, charge collection can affect multiple nodes and the SSE may not be capable of correcting errors if certain combinations of nodes are upset simultaneously. For example, SSEs are often not capable of correcting errors when a radiation strike upsets charge collection nodes coupled to inputs of a hardening element and charge collection nodes coupled to outputs of the hardening element simultaneously. Similarly, DICE may not be capable of correcting an error if the radiation strike upsets more than one of the multiple interlocked nodes simultaneously.
To prevent one ionizing track from upsetting these critical node combinations, the charge collection nodes in these critical node combinations require a minimum amount of spatial separation. Often, this minimum amount of spatial separation is provided through size increases in the SSE. Unfortunately, size increases are expensive and becoming less practical as integrated circuits (ICs) continue to become more compact. It is thus desirable that the size of the SSE be kept at a minimum, while still providing the minimum amount of spacing between critical node combinations.